Name: 'verilogCCN'
Author: 'verilogccn'

Verilog / SystemVerilog RTL development tool for VS Code — formatting, navigation, code generation, and visual drag-and-drop module interconnection.

Formatting

Format Document (Ctrl+Shift+Alt+0) — global column alignment for the entire file
Format Selection (Ctrl+Alt+0) — aligns the selected lines while preserving their original column offset within the file
Auto-detected indent — indent step is automatically detected from source (usually 2 or 4 spaces). Override with indentStep
Deep block awareness — correctly handles begin/end, generate, case, for, if/else, fork/join, function/task, always blocks, macros, and mixed single/multi-line declarations
Group alignment — ports, parameters, declarations, assignments, instances, and procedural assignments are aligned by type in consecutive groups
Continuation support — multi-line port lists, concatenation, and operator-split continuations keep proper indentation

Drag Connector

Drag-and-drop panel for interconnecting RTL modules and auto-generating a Verilog wrapper.

Add modules from the available list to Column A or B
Auto Match — ports matched by name or _i/_o suffix; parameters matched by name
Manual wiring — drag ports or parameters between columns; click to disconnect
TOP module — select one to fan out ports to sub-modules
Generate Code — produces a wrapper module with wiring, editable inline
Canvas view — switch to canvas mode to freely arrange module cards on an SVG canvas; drag ports to connect; paths auto-route around obstacles; zoom/pan with mouse

Ctrl+Click (or F12) on a module/instance name to jump to its definition (after manual scan)
Find All References — right-click a module name to locate all instantiations
RTL Hierarchy tree view in the Explorer sidebar
Filelists — .lst filelist support (-f, -y, +incdir+)
Auto-sync — after the first manual scan, file changes automatically refresh the hierarchy

Code Actions

Create Instance — right-click a module name to generate an instantiation snippet
Completion — auto-completion for Verilog keywords and indexed modules
Insert header — Ctrl+Alt+= for file header; Ctrl+Alt+] for comment header

Settings

Setting	Type	Default	Description
`verilogCCN.indentStep`	number	`4`	Spaces per indent level (2, 4, or 8)
`verilogCCN.alignModulePortPunctuation`	boolean	`true`	Align trailing comma/semicolon for module ports
`verilogCCN.alignDeclPunctuation`	boolean	`true`	Align trailing semicolon for signal declarations
`verilogCCN.alignAssignPunctuation`	boolean	`true`	Align trailing semicolon for assign statements
`verilogCCN.alignInstPunctuation`	boolean	`true`	Align trailing comma for instantiation ports
`verilogCCN.alwaysAssignPunctuation`	boolean	`true`	Align trailing semicolon for procedural assignments
`verilogCCN.alignParamPunctuation`	boolean	`true`	Align trailing comma for parameter declarations
`verilogCCN.alignCommentBreak`	boolean	`true`	Treat comment lines as group boundaries
`verilogCCN.alignCommentIndent`	boolean	`true`	Apply depth-based indentation to comment lines
`verilogCCN.filelistPath`	array	`[]`	Filelist paths to restrict indexing
`verilogCCN.indexIncludePattern`	string	`*/.{v,sv}`	Glob for files to include in module index
`verilogCCN.indexModules`	boolean	`true`	Include `module` in hierarchy
`verilogCCN.indexInterfaces`	boolean	`true`	Include `interface` in hierarchy
`verilogCCN.indexPrograms`	boolean	`true`	Include `program` in hierarchy
`verilogCCN.hierarchyShowPaths`	boolean	`false`	Show file path in hierarchy tree
`verilogCCN.headerTemplate`	string		File header template (`${fileName}`, `${date}`, etc.)
`verilogCCN.headerAuthor`	string		Default author for `${author}`
`verilogCCN.headerVersion`	string	`1.0`	Default version for `${version}`
`verilogCCN.commentHeaderTemplate`	string		Comment header template
`verilogCCN.wireSuffix`	boolean	`false`	Append `_s` to generated wire names
`verilogCCN.enableCompletion`	boolean	`true`	Enable keyword/instance completion
`verilogCCN.indexScanIntervalSeconds`	number	`30000`	Periodic full re-scan interval (0 = off)