#verilog

HDL Studio

TwinT

HDL Studio is a vscode extension for digitaljs, a digital circuit simulator.

Visual editor for WaveDrom timing-diagram JSON files.

Run Verilog

Hanying

Compile and run Verilog testbenches with Icarus Verilog and view VCD waveforms in GTKWave.

DigitalJS Schematic Viewer

VENOMNBB

Synthesises Verilog/SystemVerilog files via the DigitalJS server and renders the interactive circuit simulator directly inside VSCode.

Otter FPGA Toolkit - 水獭FPGA工具集

Otter-xiaoxiaoxuwang

小水獭的FPGA开发利器：一键例化、代码排版、iverilog/xvlog语法检查、高亮、跳转、补全

Hydra Sim Studio

RRLOGICSYSTEMSPRIVATELIMITED

VS-Code extension for simulating Verilog code.

VeriForge

LiXintao

全功能 Verilog/SystemVerilog 开发助手：Verible 格式化 & 风格检查、Verilator 语义错误检查、语法高亮、代码补全、跳转定义/hover、CodeLens、注释模板

Verilog/SystemVerilog RTL development tool: Ctrl+Click module navigation, multi-line aware column alignment, file headers

Vide — Verilog/SystemVerilog

pascal-lab

A Modern SystemVerilog Coding IDE.

LazyVerilog for VS Code

lazyverilog

SystemVerilog language support via LazyVerilog LSP

Slang Server Extended: Verilog/SystemVerilog LSP

CaioPlazas

Verilog and SystemVerilog support via an extended fork of the slang language server, with support for unusual/ASIC project configurations (workDir, recursive incdirs, include-fragment resolution, a bundled Linux binary, and more). Fork of hudson-trading/slang-server.

EDA Job Runner

CaioPlazas

Tool-agnostic sidebar for running and tracking EDA compile/simulation jobs (Xcelium, Questa, or any custom script) without leaving VS Code.