#systemverilog

DigitalJS Schematic Viewer

VENOMNBB

Synthesises Verilog/SystemVerilog files via the DigitalJS server and renders the interactive circuit simulator directly inside VSCode.

Otter FPGA Toolkit - 水獭FPGA工具集

Otter-xiaoxiaoxuwang

小水獭的FPGA开发利器：一键例化、代码排版、iverilog/xvlog语法检查、高亮、跳转、补全

VeriForge

LiXintao

全功能 Verilog/SystemVerilog 开发助手：Verible 格式化 & 风格检查、Verilator 语义错误检查、语法高亮、代码补全、跳转定义/hover、CodeLens、注释模板

Verilog/SystemVerilog RTL development tool: Ctrl+Click module navigation, multi-line aware column alignment, file headers

Vide — Verilog/SystemVerilog

pascal-lab

A Modern SystemVerilog Coding IDE.

LazyVerilog for VS Code

lazyverilog

SystemVerilog language support via LazyVerilog LSP

Slang Server Extended: Verilog/SystemVerilog LSP

CaioPlazas

Verilog and SystemVerilog support via an extended fork of the slang language server, with support for unusual/ASIC project configurations (workDir, recursive incdirs, include-fragment resolution, a bundled Linux binary, and more). Fork of hudson-trading/slang-server.

EDA Job Runner

CaioPlazas

Tool-agnostic sidebar for running and tracking EDA compile/simulation jobs (Xcelium, Questa, or any custom script) without leaving VS Code.

SiliCode: HDL AI

silicode

AI-powered Verilog, SystemVerilog, and VHDL RTL generation in VS Code — powered by the SiliCode AI.

CovSight

covsight

Navigate and understand functional coverage data from UCIS NCDB databases

HDL BlockSeal

VENOMNBB

Auto-inserts closing keywords (endmodule, end, endfunction, etc.) when you press Enter at the end of an opening block line. Supports Verilog, SystemVerilog, and VHDL.

FormalOS VP Creator

formalos

Author and track LUBIS EDA formal verification plans — goals, requirements, tasks, milestones and comments — without leaving VS Code.