#fpga

VHDL Essentials

Guizzz

Complete Quartus workflow: build, flash, simulate. VHDL linting, navigation, pin diagnostics, QSF integration.

VeriForge

LiXintao

全功能 Verilog/SystemVerilog 开发助手：Verible 格式化 & 风格检查、Verilator 语义错误检查、语法高亮、代码补全、跳转定义/hover、CodeLens、注释模板

Slang Server Extended: Verilog/SystemVerilog LSP

CaioPlazas

Verilog and SystemVerilog support via an extended fork of the slang language server, with support for unusual/ASIC project configurations (workDir, recursive incdirs, include-fragment resolution, a bundled Linux binary, and more). Fork of hudson-trading/slang-server.

EDA Job Runner

CaioPlazas

Tool-agnostic sidebar for running and tracking EDA compile/simulation jobs (Xcelium, Questa, or any custom script) without leaving VS Code.

Qsys View

YaroslavMariukha

Explore Intel Platform Designer .qsys systems, exported Tcl scripts, and *_hw.tcl components as readable layered graphs.

Fizzim FSM Editor

CaioPlazas

Draw finite state machines and generate synthesizable Verilog/VHDL — a native VS Code editor for Fizzim (.fzm) diagrams.

SiliCode: HDL AI

silicode

AI-powered Verilog, SystemVerilog, and VHDL RTL generation in VS Code — powered by the SiliCode AI.

NextMicon VSCode Extension

kanade-k-1228

Visual FPGA circuit editor for NextMicon projects

Clash Toolkit

LucasBollen

Community extension for Clash: synthesize, view schematics, and place-and-route Haskell hardware designs with Yosys and nextpnr.